A Flexible FPGA-Based Quasi-Cyclic LDPC Decoder
نویسندگان
چکیده
منابع مشابه
A Memory Efficient FPGA Implementation of Quasi-Cyclic LDPC Decoder
Low-Density Parity-Check (LDPC) code is one kind of prominent error correcting codes (ECC) being considered in next generation industry standards. The decoder implementation complexity has been the bottleneck of its application. This paper presents an implementation of Quasi-Cyclic Low-Density Parity-Check decoder by using FPGA. Modified Min-Sum decoding algorithm is applied to reduce the memor...
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ژورنال
عنوان ژورنال: IEEE Access
سال: 2017
ISSN: 2169-3536
DOI: 10.1109/access.2017.2678103